MATLAB FIXED-POINT TOOLBOX - RELEASE NOTES Guide de l'utilisateur Page 35
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System Generator for DSP Getting Started Guide www.xilinx.com 35
UG639 (v 12.2) July 23, 2010
Release Notes 11.4
Release Notes 11.4
System Generator Enhancements
New Device Support
• Spartan®-6 Low Power
• Spartan-6 XA
New Platform Support
System Generator now supports Ethernet Hardware Co-Simulation for the Virtex®-6
ML605 Platform
Xilinx Blockset Enhancements
New Blocks
DSP48 Macro 2.0
New block now available in System Generator with the following features:
• The primary change is that the DSP48 Macro block is now supported by an
underlying LogiCORE rather than being a System Generator basic block.
• Expanded instruction functionality coverage with the addition of 77 new opcode
instructions, bringing the opcode count from 72 to 149.
• Additional pipelining capability with the addition of Opmode, M Reg, and P Reg
Stages. The Macro supports three latency modes (Automatic, By Tier, and Expert).
Automatic and tiered are square latency models, the difference being that automatic
gives a fully pipelined model where as tiered allows for finer control.
• Reset & Enable Ports: DSP Macro v2.0 provides a global sclr (rst in System Generator)
and ce (en in System Generator) and does not provide access to individual enable and
reset ports of various registers in the XtremeDSP slice.
• Support for Pre-Adder in Virtex
®-6, Spartan®-6 and Spartan-3A DSP families,
including the Pre-Adder D Port.
• Support for various rounding capabilities.
• Now support up to 64 instructions, up from 8 in the previous System Generator block.
Existing Block Updates
The following blocks have been updated with the features mentioned below.
Complex Multiplier 3.1
• Support added for Spartan-6L and Spartan-6 XA
• Option added to configure latency.
Note:
This block supersedes the Complex Multiplier 3.0 block
Convolution Encoder 7.0
• Support added for Virtex-6 and Spartan-6
- Generator for 1
- Table of Contents 3
- Chapter 4: Getting Started 4
- About This Guide 7
- Additional Resources 8
- Conventions 8
- Online Document 9
- Preface: About This Guide 10
- Introduction 11
- The Xilinx DSP Block Set 12
- FIR Filter Generation 13
- Support for MATLAB 14
- System Resource Estimation 15
- Hardware Co-Simulation 16
- System Integration Platform 17
- Chapter 1: Introduction 18
- Installation 19
- Chapter 2: Installation 20
- Table 2-3: 20
- Table 2-4: 20
- UNC Paths Not Supported 21
- Software Prerequisites 21
- Post Installation Tasks 22
- UG639 (v 12.2) July 23, 2010 23
- ModelSim SE 24
- Setting the Size 25
- Setting the Number of Entries 25
- Release Information 27
- Hardware Recommendations 28
- Known Issues 29
- Release Notes 12.1 30
- Xilinx Blockset Enhancements 31
- Release Notes 11.4 35
- Table 3-5: 37
- Table 3-6: 37
- Release Notes 11.3 39
- Existing Block Updates 40
- Table 3-7: 41
- Table 3-8: 41
- Getting Started 43
- ® Simulator 44
- The Xilinx DSP Blockset 45
- Defining the FPGA Boundary 46
- Creating the DSP Design 48
- Generating the HDL Code 49
- Chapter 4: Getting Started 50
- DSP blockset 50
- Lesson 1 Summary 52
- Lab Exercise: Using Simulink 52
- Fixed-Point Numeric Precision 53
- Overflow and Round Modes 55
- Bit-Level Operations 56
- The Reinterpret Block 57
- The Convert Block 58
- The Concat Block 59
- Slice Block 60
- The BitBasher Block 61
- Lesson 2 Summary 62
- Lab Exercise: Signal Routing 62
- Lesson 3 - System Control 63
- The MCode Block 64
- State Machine Example 66
- The Expression Block 67
- Reset and Enable Ports 68
- Bursty Data 69
- Lesson 3 Summary 70
- Lab Exercise: System Control 70
- Lesson 4 - Multi-Rate Systems 71
- Up and Down Sampling Blocks 72
- Debugging Tools 75
- Sample Period “Rules” 76
- Lesson 5 - Using Memories 78
- Initializing RAMs and ROMs 79
- System Generator RAM Blocks 80
- System Generator ROM Blocks 81
- The Delay Block 82
- The FIFO Block 83
- Shared Memory Block 84
- Lab Exercise: Using Memories 85
- Lesson 6 - Designing Filters 86
- The Virtex DSP48 Math Slice 87
- FIR Compiler Block 88
- Using FDA Tool Coefficients 90
- Virtex®-5 architecture 91
- Black Box Examples 92
- ChipScope Examples 92
- DSP Examples 93
- M-Code Examples 94
- Processor Examples 94
- Shared Memory Examples 95
- Timing Analysis Examples 96
- Miscellaneous Examples 96
- System Generator Demos 97
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