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38 DSP Selection Guide

ADSP-21160

Single-Instruction, Multiple-Data (SIMD) SHARC

®

http://www.analog.com/dsp

Features

• 540 MFLOPS (32-bit floating-point) peak

operation

• 540 MOPS (32-bit fixed-point) peak operation

• 90 MHz core operation, 11 ns cycle time

• 92 µs 1024-point comlex FFT benchmark

with bit reversal

• Code compatible with first generation

SHARC

• SIMD core includes 2 multipliers, 2 ALUs,

2 shifters, and 2 register files

• 4 Mbits on-chip dual-ported SRAM

• Division of SRAM between program and

data memory is selectable

• Core can fetch four 32-bit words from mem-

ory in a single processor cycle using two

64-bit wide buses

• Dual data address generators with modulo

and bit-reverse addressing

• Efficient program sequencing with zero-over-

head looping—single-cycle loop setup

• IEEE JTAG standard 1149.1 test access port

and on-chip emulation

• 32-bit single-precision IEEE floating-point

data type and 40-bit extended precision

floating-point data type support

• 32-bit fixed-point formats, integer and frac-

tional, with 80-bit accumulators in both pro-

cessing elements

• 14 channels of zero-overhead DMA

• Glueless connection for scaleable DSP

multiprocessing architectures

• Distributed on-chip bus arbitration for parallel

bus connect of up to six ADSP-21160s plus

host

• Six 100 Mbytes/sec link ports for point-to-

point connectivity and array multi-processing

• 2.5 volt core, 3.3 volt I/O (80 MHz

ADSP-21160M)

• 1.9 volt core, 3.3 volt I/O (95 MHz

ADSP-21160N)

Applications

• Cellular base stations

• Call processing

• Speech recognition

• Instrumentation

• 3D graphics acceleration for workstations

and arcade video games

• Imaging

• High-end audio

• Radar and sonar

Development Tools

ADDS-2116X-WKSHP

ADDS-21160-EZLITE

ADDS-21160N-EZLITE

VDSP-SHARC-PC-FULL

VDSP-SHARC-PCFLOAT

ADDS-APEX-ICE

ADDS-SUMMIT-ICE

DSP Workshop

Evaluation Kit for “M”

Evaluation Kit for “N”

VisualDSP++

VisualDSP++ Floating License

USB-Based Emulator

PCI-Based Emulator

I/O Processor

External Port

Core Processor Dual-Ported SRAM

Addr

DAG1

8 x 4 x 32

Program

Sequencer

Instruction

Cache

32 x 48-Bit

DAG2

8 x 4 x 32

Two Independent

Dual-Ported Blocks

Timer

Bus

Connect

(PX)

Addr

Data

Data

Data

Data

Addr

Addr

Processor Port I/O Port

Block 0

Block 1

IOD

64

IOA

32

32

PM Address Bus

DM Address Bus

32

Address

Mux

Bus

32

Data

Mux

Bus

64

Multiprocessor

Interface

Host Port

DMA

Controller

4

Serial Ports

(2)

6

60

Link Ports

(6)

6

IOP

Registers

(Memory

Mapped)

Control,

Status, and

Data Buffers

Data

Register

File

(PEx)

16 x 40-Bit

Mult

Barrel

Shifter

ALU

Data

Register

File

(PEy)

16 x 40-Bit

Mult

Barrel

Shifter

ALU

32/48/64

PM Data Bus

DM Data Bus

32/40/64

JTAG

Test and

Emulation

7

ADSP-21160MKB-80

ADSP-21160NKB-95

80

95

400-PBGA

400-PBGA

$145.00

$145.00

M indicates 2.5V operation

N indicates 1.9V operation

K = Commercial Temp (0ºC to +85ºC case)

* All pricing is budgetary – subject to change

Model MHz Pin/Pkg

(1000)

Price*

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 61 62

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