MATLAB DESIGN HDL CODER RELEASE NOTES Guide de l'utilisateur Page 104
- Page / 410
- Table des matières
- DEPANNAGE
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
104 www.xilinx.com System Generator for DSP User Guide
UG640 (v 12.2) July 23, 2010
Chapter 1: Hardware Design Using System Generator
DSP48 Macro 2.0-Based Signed 35x35 Multiplier
The same model shown above can be migrated to the new DSP48 Macro 2.0 block. The
following simple steps and design guidelines are required when updating the design.
1. Make sure that input and output pipeline register selections between the old and the
new block are the same. You can do this by examining and comparing the Pipeline
Options settings.
2. If there is more than one unique input operand required, you must provide MUX
circuits as shown in the fugure below.
3. Ensure that the new design provides the same functionality correctness and quality of
results compared to the old version. This can be accomplished by performing a quick
Simulink simulation and implementing the design.
4. When configuring and specifying a pre-adder mode using the DSP48 Macro 2.0 block
in System Generator, certain design parameters such as data width input operands are
device dependent. Refer to the LogiCORE IP DSP48 Macro v2.0 Product Specification
for details on all the parameters on this LogicCore IP.
- Generator for 1
- Table of Contents 3
- About This Guide 9
- Conventions 10
- Preface: About This Guide 12
- Hardware Design Using System 13
- Generator 13
- A Brief Introduction to FPGAs 14
- Note to the DSP Engineer 18
- Note to the Hardware Engineer 18
- Algorithm Exploration 19
- System Generator Blocksets 21
- Xilinx Blockset 22
- Xilinx Reference Blockset 22
- Signal Types 23
- Timing and Clocking 24
- Rate-Changing Blocks 25
- Multirate Models 25
- Hardware Oversampling 26
- Asynchronous Clocking 26
- Synchronous Clocking 26
- The Clock Enables Option 27
- The Hybrid DCM-CE Option 27
- The Expose Clock Ports Option 28
- Synchronization Mechanisms 36
- Block Masks 37
- Parameter Passing 37
- Automatic Code Generation 39
- Simulink System Period 43
- Block Icon Display 43
- Viewing ISE Reports 44
- Compilation Results 44
- System Clock Period 46
- Multicycle Path Constraints 46
- Constraints Example 47
- Clock Handling in HDL 48
- HDL Testbench 50
- Compiling MATLAB into an FPGA 51
- Simple Arithmetic Operations 52
- Shift Operations 56
- Optional Input Ports 60
- Finite State Machines 62
- Parameterizable Accumulator 63
- RPN Calculator 69
- Example of disp Function 71
- Integration Design Rules 73
- A Step-by-Step Example 75
- Simulating the Entire Design 80
- Design Tools 90
- Generating an FPGA Bitstream 93
- Implementing Your Design 94
- Table 1-1: 97
- DSP48 Block 101
- Dynamic Control of the DSP48 101
- DSP48 Macro Block 102
- UG640 (v 12.2) July 23, 2010 103
- Design Styles for the DSP48 105
- DSP48 Design Techniques 106
- C-Input Sharing 107
- Adder Trees Planning 107
- Placement 107
- Signal Length Planning 107
- Cascade Routing Buses 107
- Design Overview 110
- Run the Simulation 115
- Multiple Clock Applications 118
- Clock Domain Partitioning 119
- Crossing Clock Domains 120
- Step-by-Step Example 122
- Creating a Top-Level Wrapper 126
- ChipScope Pro Overview 130
- Real-Time Debug 135
- Bus Plot 137
- Co-Simulation 140
- Benefits 141
- Pro Analyzer 141
- Hardware/Software Co-Design 143
- Black Box Block 144
- PicoBlaze Block 144
- EDK Processor Block 144
- Memory Map Creation 146
- Hardware Generation 147
- Hardware Co-Simulation 147
- The Software Driver 148
- API Documentation 150
- Writing a Software Program 151
- Single-Word Reads 152
- Single-Word Writes 152
- Asynchronous Support 154
- Dual Clock Wiring Scheme 156
- Single Clock Wiring Scheme 158
- Troubleshooting 161
- EDK Support 163
- EDK Import Wizard 164
- Limitations 164
- Exporting a pcore 166
- Architecture Highlights 167
- 16 General Purpose Registers 167
- Flags and Program Control 168
- Input/Output 168
- Interrupt 168
- Write Software 176
- Create an XPS Project 179
- Import the XPS Project 180
- Write Software Programs 181
- Create a Testbench Model 184
- Using XPS 186
- Using Platform Studio SDK 191
- Embedded DSP Design 200
- Objectives 201
- Tutorial Exercise Setup 201
- Design Description 202
- PROCEDURE 203
- Hardware Co-Simulation Block 207
- Using Hardware Co-Simulation 225
- Choosing a Compilation Target 227
- Invoking the Code Generator 227
- Hardware Co-Simulation Blocks 228
- 2. Select 231
- 1. Click 231
- Clocking Modes 232
- Selecting the Clock Mode 232
- Board-Specific I/O Ports 233
- Interface Features 235
- Co-Simulating the Design 238
- Known Issues 239
- Setup Procedures 239
- Specifying the Cable Location 240
- Starting Up a CSE server 241
- Shared Memory Support 242
- Compiling Shared Memory Pairs 244
- Memory Type Icon 245
- Shared Memory 245
- Shared FIFO 245
- Shared Register 245
- Co-Simulating Shared FIFOs 249
- Shared Memories 254
- Adding Buffers to a Design 256
- Using Vector Transfers 262
- Valid Bit Generation 270
- 5x5 Filter Kernel Test Bench 272
- Reloading the Kernel 276
- ®/Simulink software from The 277
- Setup the PC 281
- Setup the ML402 board 282
- Install Related Software 286
- Setup the Local Area Network 286
- Setup the ML506 board 287
- System ACE™ Reset 290
- Setup the ML605 board 291
- Simulation 294
- Setup the SP601/SP605 Board 299
- Setup the ML402 Board 301
- Setup the ML605 Board 303
- Hardware Requirements 307
- Supporting New Boards 307
- SBDBuilder Dialog Box 308
- Saving Plugin Files 312
- Board Support Package Files 313
- Providing Your Own Top Level 317
- Plugins Directory 318
- Detecting New Packages 319
- Importing HDL Modules 321
- Language Selection 325
- Defining Block Ports 326
- Port Object 326
- Port Types 327
- Configuring Port Sample Rates 328
- Dynamic Output Ports 328
- Black Box Clocking 329
- Combinational Paths 330
- Error Checking 331
- Black Box API 331
- SysgenBlockDescriptor Methods 332
- SysgenPortDescriptor Methods 334
- HDL Co-Simulation 335
- ModelSim Simulator 336
- Black Box Examples 338
- /coregen_import_example2.cgp 345
- Click Next > 347
- Importing a VHDL Module 352
- Importing a Verilog Module 359
- Dynamic Black Boxes 361
- Simultaneously 363
- ModelSim 366
- Encrypted VHDL File 370
- Chapter 5 377
- HDL Netlist Compilation 378
- NGC Netlist Compilation 378
- Bitstream Compilation 379
- XFLOW Option Files 380
- Additional Settings 381
- EDK Export Tool 383
- Export as Pcore to EDK 385
- See Also: 386
- Period and Slack 389
- Path Analysis Example 389
- Timing Analyzer Features 390
- Cross-Probing 391
- Histogram Charts 392
- Histogram Detail 394
- Statistics 394
- Trace Report 394
- Improving Failing Paths 395
- Generate the Example Design 398
- Examine the Slow Paths 398
- Rescue the Design 399
- Creating Compilation Targets 401
- The xltarget Function 402
- Target Info Functions 403
- Using XFLOW 405
Produits connexes et manuels pour Logiciel MATLAB DESIGN HDL CODER RELEASE NOTES
Sony SLT-A65VL Handbücher
Bedienungsanleitungen und Benutzerhandbücher für CD Spieler Sony SLT-A65VL.
Wir stellen PDF-Handbücher Sony SLT-A65VL zum kostenlosen herunterladen nach Dokumenttypen zur Verfügung
Weitere Produkte und Handbücher für CD Spieler Sony
| Modelle | Dokumententyp |
|---|---|
| CDX-V58MP |
Bedienungsanleitung
Sony CDX-V58MP User's Manual,
4 Seiten
|
| D-VJ85 |
Bedienungsanleitung
Sony D-VJ85 User manual,
36 Seiten
|
| MDX-C8900R |
Bedienungsanleitung
 
Sony MDX-C8900R Manual de usuario,
186 Seiten
|
| HDX266/HDX267W |
Bedienungsanleitung
Sony HDX266/HDX267W User's Manual,
104 Seiten
|
| CDX-M10 |
Betriebsanleitung
   
Sony CDX-M10 Operating Instructions,
116 Seiten
|
| MEX-BT2700 |
Bedienungsanleitung
Sony MEX-BT2700 User's Manual,
56 Seiten
|
| CDP-M555ES |
Bedienungsanleitung
Sony CDP-M555ES User's Manual,
48 Seiten
|
| CDX-M30 |
Bedienungsanleitung
Sony CDX-M30 User's Manual,
144 Seiten
|
| D-E660 |
Bedienungsanleitung
Sony D-E660 User's Manual,
32 Seiten
|
| D-MJ95 |
Bedienungsanleitung
Sony D-MJ95 User manual,
28 Seiten
|
| D-F21 |
Bedienungsanleitung
Sony D-F21 User manual,
24 Seiten
|
| D-E561 |
Bedienungsanleitung
Sony D-E561 User's Manual,
2 Seiten
|
| CDX-434RF |
Bedienungsanleitung
Sony CDX-434RF User manual,
4 Seiten
|
| CDP-CX335 |
Bedienungsanleitung
Sony CDP-CX335 User manual,
68 Seiten
|
| D-E551 |
Bedienungsanleitung
Sony D-E555 User manual,
2 Seiten
|
| CDX-C910 |
Bedienungsanleitung
Sony CDX-C910 User manual,
62 Seiten
|
| HAR-D1000 |
Bedienungsanleitung
Sony HAR-D1000 User's Manual,
36 Seiten
|
| CFD-360 |
Bedienungsanleitung
Sony CFD-360 User manual,
60 Seiten
|
| D-SJ01 |
Bedienungsanleitung
Sony D-SJ01 User manual,
24 Seiten
|
| CFD-577 |
Bedienungsanleitung
Sony CFD-577 User manual,
36 Seiten
|
© 2020, manymanuals.fr. Tous droits réservés | 0.027 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Commentaires sur ces manuels