MATLAB EMBEDDED IDE LINK 4 - FOR USE WITH TEXAS INSTRUMENTS CODE COMPOSER STUDIO Guide de l'utilisateur Page 467

  • Télécharger
  • Ajouter à mon manuel
  • Imprimer
  • Page
    / 575
  • Table des matières
  • MARQUE LIVRES
  • Noté. / 5. Basé sur avis des utilisateurs
Vue de la page 466
Targ et Preferences
Master clock H igh -time divider
When Mode is
Master, this divider determines the duration
of the high state on the serial clock pin (SCL) of the I2C-bus.
The high-time duration of the m aster clock = T mod x (ICCL
+d).
For more information about this value, consult the “Formula
for the Master Clock Period” section in the TMS320x280x
Inter-Integrated Circuit Module Reference Guide,Literature
Number: SPRU721A, available on the Texas Instruments
Web site.
This parameter corresponds to bits 15–0 (ICCH) of the C lock
High-Time Divider Register (I2CCLKH).
Enable loopback
When Mode is
Master, enable or disable digital loopback
mode. In digital loopback mode, I2CDXR transmits data
over an internal path to I2CDRR, w hich receives the data
after a congurable delay. The delay, measured in DSP
cycles, equals (I2C input clock frequency/module clock
frequency) x 8.
While Enable loopback is enabled, free data format
addressing is not supported.
This parameter corresponds to bit 6 (DLB) of the I2C Mode
Register (I2CMDR).
Enable Tx Interrupt
This parameter corresponds to bit 5 (TXFFIENA) of the I2C
Transmit FIFO R egister (I2CFFTX).
Tx FIFO interrupt level
This parameter corresponds to bits 4–0 (TXFFIL4-0) of the
I2C Transmit FIFO R egister (I2CFFTX).
9-75
Vue de la page 466
1 2 ... 462 463 464 465 466 467 468 469 470 471 472 ... 574 575

Commentaires sur ces manuels

Pas de commentaire