MATLAB SIMULINK HDL CODER - RELEASE NOTES Guide de l'utilisateur

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System
Generator for
DSP
Getting Started Guide
UG639 (v 14.3) October 16, 2012
This document applies to the following software versions: ISE Design Suite 14.3 through 14.5This document applies to the following software versions: ISE Design Suite 14.3 through 14.5This document applies to the following software versions: ISE Design Suite 14.3 through 14.5This document applies to the following software versions: ISE Design Suite 14.3 through 14.5
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Résumé du contenu

Page 1 - Generator for

System Generator for DSPGetting Started GuideUG639 (v 14.3) October 16, 2012This document applies to the following software versions: ISE Design Suite

Page 2

10 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 1: IntroductionSupport for MATLABIncluded in Sy

Page 3 - Table of Contents

System Generator for DSP Getting Started Guide www.xilinx.com 11UG639 (v 14.3) October 16, 2012System Resource EstimationSystem Resource EstimationSys

Page 4

12 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 1: IntroductionHardware Co-SimulationSystem Gen

Page 5

System Generator for DSP Getting Started Guide www.xilinx.com 13UG639 (v 14.3) October 16, 2012System Integration PlatformSystem Integration PlatformS

Page 6

14 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 1: Introduction

Page 7 - Introduction

System Generator for DSP Getting Started Guide www.xilinx.com 15UG639 (v 14.3) October 16, 2012Chapter 2InstallationDownloadingSystem Generator is par

Page 8 - The Xilinx DSP Block Set

16 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 2: InstallationUsing the ISE Design Suite Insta

Page 9 - FIR Filter Generation

System Generator for DSP Getting Started Guide www.xilinx.com 17UG639 (v 14.3) October 16, 2012Post Installation TasksIf MATLAB is configured for a De

Page 10 - Support for MATLAB

18 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 2: InstallationCould not find ml_supported.xml

Page 11 - System Resource Estimation

System Generator for DSP Getting Started Guide www.xilinx.com 19UG639 (v 14.3) October 16, 2012Post Installation TasksInstalling an SP601/SP605 Board

Page 12 - Hardware Co-Simulation

System Generator for DSP Getting Started Guide www.xilinx.com UG639 (v 14.3) October 16, 2012Xilinx is disclosing this user guide, manual, release not

Page 13 - System Integration Platform

20 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 2: InstallationSetting the Number of EntriesThe

Page 14 - Chapter 1: Introduction

System Generator for DSP Getting Started Guide www.xilinx.com 21UG639 (v 14.3) October 16, 2012Chapter 3Release InformationSystem Generator for DSP re

Page 15 - Installation

22 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 3: Release Information

Page 16 - Windows Installations

System Generator for DSP Getting Started Guide www.xilinx.com 23UG639 (v 14.3) October 16, 2012Chapter 4Getting StartedIntroductionThis Getting Starte

Page 17 - Post Installation Tasks

24 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedLesson 1 - Design Creation Ba

Page 18

System Generator for DSP Getting Started Guide www.xilinx.com 25UG639 (v 14.3) October 16, 2012Lesson 1 - Design Creation BasicsThe Xilinx DSP Blockse

Page 19 - Setting the Size

26 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedDefining the FPGA BoundarySys

Page 20 - Setting the Number of Entries

System Generator for DSP Getting Started Guide www.xilinx.com 27UG639 (v 14.3) October 16, 2012Lesson 1 - Design Creation BasicsAdding the System Gene

Page 21 - Release Information

28 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedCreating the DSP DesignOnce t

Page 22

System Generator for DSP Getting Started Guide www.xilinx.com 29UG639 (v 14.3) October 16, 2012Lesson 1 - Design Creation BasicsGenerating the HDL Cod

Page 23 - Getting Started

System Generator for DSP Getting Started Guide www.xilinx.com 3UG639 (v 14.3) October 16, 2012Chapter 1: IntroductionThe Xilinx DSP Block Set . . .

Page 24 - ® Simulator

30 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedModel-Based Design using Syst

Page 25 - The Xilinx DSP Blockset

System Generator for DSP Getting Started Guide www.xilinx.com 31UG639 (v 14.3) October 16, 2012Lesson 1 - Design Creation BasicsCreating Input Vectors

Page 26 - Defining the FPGA Boundary

32 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedLesson 1 Summary• You partiti

Page 27

System Generator for DSP Getting Started Guide www.xilinx.com 33UG639 (v 14.3) October 16, 2012Lesson 2 - Fixed Point and Bit OperationsLesson 2 - Fix

Page 28 - Creating the DSP Design

34 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedSystem Generator Fixed-Point

Page 29 - Generating the HDL Code

System Generator for DSP Getting Started Guide www.xilinx.com 35UG639 (v 14.3) October 16, 2012Lesson 2 - Fixed Point and Bit OperationsOverflow and R

Page 30 - DSP blockset

36 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedBit-Level OperationsIn a real

Page 31

System Generator for DSP Getting Started Guide www.xilinx.com 37UG639 (v 14.3) October 16, 2012Lesson 2 - Fixed Point and Bit OperationsThe Reinterpre

Page 32 - Lab Exercise: Using Simulink

38 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedThe Convert BlockThe Convert

Page 33 - Fixed-Point Numeric Precision

System Generator for DSP Getting Started Guide www.xilinx.com 39UG639 (v 14.3) October 16, 2012Lesson 2 - Fixed Point and Bit OperationsThe Concat Blo

Page 34

4 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012The Reinterpret Block . . . . . . . . . . . . . . . . .

Page 35 - Overflow and Round Modes

40 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedSlice BlockThe Slice block is

Page 36 - Bit-Level Operations

System Generator for DSP Getting Started Guide www.xilinx.com 41UG639 (v 14.3) October 16, 2012Lesson 2 - Fixed Point and Bit OperationsThe BitBasher

Page 37 - The Reinterpret Block

42 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedLesson 2 Summary• Quantizatio

Page 38 - The Convert Block

System Generator for DSP Getting Started Guide www.xilinx.com 43UG639 (v 14.3) October 16, 2012Lesson 3 - System ControlLesson 3 - System ControlContr

Page 39 - The Concat Block

44 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedThe MCode BlockThe MCode bloc

Page 40 - Slice Block

System Generator for DSP Getting Started Guide www.xilinx.com 45UG639 (v 14.3) October 16, 2012Lesson 3 - System ControlThe Xilinx “xl_state” Data Typ

Page 41 - The BitBasher Block

46 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedState Machine ExampleThe figu

Page 42 - Lab Exercise: Signal Routing

System Generator for DSP Getting Started Guide www.xilinx.com 47UG639 (v 14.3) October 16, 2012Lesson 3 - System ControlThe Expression BlockThe Expres

Page 43 - Lesson 3 - System Control

48 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedReset and Enable PortsMost Sy

Page 44 - The MCode Block

System Generator for DSP Getting Started Guide www.xilinx.com 49UG639 (v 14.3) October 16, 2012Lesson 3 - System ControlBursty DataSeveral of the more

Page 45

System Generator for DSP Getting Started Guide www.xilinx.com 5UG639 (v 14.3) October 16, 2012Index . . . . . . . . . . . . . . . . . . . . . . . . .

Page 46 - State Machine Example

50 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedLesson 3 Summary• Use the MCo

Page 47 - The Expression Block

System Generator for DSP Getting Started Guide www.xilinx.com 51UG639 (v 14.3) October 16, 2012Lesson 4 - Multi-Rate SystemsLesson 4 - Multi-Rate Syst

Page 48 - Reset and Enable Ports

52 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedUp and Down Sampling BlocksSy

Page 49 - Bursty Data

System Generator for DSP Getting Started Guide www.xilinx.com 53UG639 (v 14.3) October 16, 2012Lesson 4 - Multi-Rate SystemsRate Changing Functional B

Page 50 - Lab Exercise: System Control

54 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedViewing Rate Changes in Simul

Page 51 - Lesson 4 - Multi-Rate Systems

System Generator for DSP Getting Started Guide www.xilinx.com 55UG639 (v 14.3) October 16, 2012Lesson 4 - Multi-Rate SystemsDebugging ToolsSystem Gene

Page 52 - Up and Down Sampling Blocks

56 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedSample Period “Rules”The illu

Page 53

System Generator for DSP Getting Started Guide www.xilinx.com 57UG639 (v 14.3) October 16, 2012Lesson 4 - Multi-Rate SystemsLab Exercise: Multi-Rate S

Page 54

58 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedLesson 5 - Using MemoriesBloc

Page 55 - Debugging Tools

System Generator for DSP Getting Started Guide www.xilinx.com 59UG639 (v 14.3) October 16, 2012Lesson 5 - Using MemoriesInitializing RAMs and ROMsThe

Page 56 - Sample Period “Rules”

6 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012

Page 57

60 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedSystem Generator RAM BlocksSy

Page 58 - Lesson 5 - Using Memories

System Generator for DSP Getting Started Guide www.xilinx.com 61UG639 (v 14.3) October 16, 2012Lesson 5 - Using MemoriesSystem Generator ROM BlocksThe

Page 59 - Initializing RAMs and ROMs

62 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedThe Delay BlockThe Delay bloc

Page 60 - System Generator RAM Blocks

System Generator for DSP Getting Started Guide www.xilinx.com 63UG639 (v 14.3) October 16, 2012Lesson 5 - Using MemoriesThe FIFO BlockThe FIFO block s

Page 61 - System Generator ROM Blocks

64 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedShared Memory BlockSystem Gen

Page 62 - The Delay Block

System Generator for DSP Getting Started Guide www.xilinx.com 65UG639 (v 14.3) October 16, 2012Lesson 5 - Using MemoriesLab Exercise: Using MemoriesIn

Page 63 - The FIFO Block

66 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedLesson 6 - Designing FiltersI

Page 64 - Shared Memory Block

System Generator for DSP Getting Started Guide www.xilinx.com 67UG639 (v 14.3) October 16, 2012Lesson 6 - Designing FiltersThe Virtex DSP48 Math Slice

Page 65 - Lab Exercise: Using Memories

68 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedFIR Compiler BlockThe Xilinx

Page 66 - Lesson 6 - Designing Filters

System Generator for DSP Getting Started Guide www.xilinx.com 69UG639 (v 14.3) October 16, 2012Lesson 6 - Designing FiltersCreating Coefficients with

Page 67 - The Virtex DSP48 Math Slice

System Generator for DSP Getting Started Guide www.xilinx.com 7UG639 (v 14.3) October 16, 2012Chapter 1IntroductionSystem Generator is a DSP design to

Page 68 - FIR Compiler Block

70 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedUsing FDA Tool CoefficientsOn

Page 69

System Generator for DSP Getting Started Guide www.xilinx.com 71UG639 (v 14.3) October 16, 2012Lesson 6 - Designing FiltersLab Exercise: Designing Fil

Page 70 - Using FDA Tool Coefficients

72 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedAdditional Examples and Tutor

Page 71 - Virtex®-5 architecture

System Generator for DSP Getting Started Guide www.xilinx.com 73UG639 (v 14.3) October 16, 2012Additional Examples and TutorialsChipScope ExamplesDSP

Page 72 - Black Box Examples

74 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedM-Code ExamplesMAC FIR filter

Page 73 - DSP Examples

System Generator for DSP Getting Started Guide www.xilinx.com 75UG639 (v 14.3) October 16, 2012Additional Examples and TutorialsProcessor ExamplesShar

Page 74 - M-Code Examples

76 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting StartedMiscellaneous ExamplesTopic D

Page 75 - Shared Memory Examples

System Generator for DSP Getting Started Guide www.xilinx.com 77UG639 (v 14.3) October 16, 2012Additional Examples and TutorialsSystem Generator Demos

Page 76 - Miscellaneous Examples

78 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 4: Getting Started

Page 77 - System Generator Demos

System Generator for DSP Getting Started Guide www.xilinx.com 79UG639 (v 14.3) October 16, 2012BBlock Colormeaning of block backgorund color 25CColor

Page 78

8 www.xilinx.com System Generator for DSP Getting Started GuideUG639 (v 14.3) October 16, 2012Chapter 1: IntroductionThe Xilinx DSP Block SetOver 90 D

Page 79

System Generator for DSP Getting Started Guide www.xilinx.com 9UG639 (v 14.3) October 16, 2012FIR Filter GenerationFIR Filter GenerationSystem Generat

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