MATLAB SIMULINK HDL CODER 1 Manuel d'utilisateur télécharger pdf (Page 33)

9/21/2011

Summary: Code Generation Optimizations

 Shorter iteration cycles

–

Automatic HDL code generation

Automatic

HDL

code

generation

 Flexible automatic HDL Code generation

– Speed Optimization

– Area Optimization

– Make the right design choices to save power

–

Analyze implementation results, resource utilization report

Analyze

implementation

results,

resource

utilization

report

– Validation models to prove that implementation is correct

Agenda

9:45

Welcome

10:00

Reduce FPGA Develo

ment Time with Model-Based Desi

11:00

Break

11:15

Integrated HDL Verification

12:00

Xilinx Target-optimized FPGA Design Using MATLAB and Simulink

13:15

Lunch

13:15

Lunch

14:15

FPGA Design Optimization Techniques

15:45

Q&A, Summary and Wrap-up

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 45 46

9/21/2011 1
Introducing The Speakers 2
MathWorks and Xilinx Goals 2
MathWorks at a Glance 3
MathWorks Today 3
Key Industries 4
Who is Who??? 4
(A Brief Example) 5
Why do we use FPGAs? 7
Why Model-Based Design? 12
Flexible Design Environment 15
Fixed Point Analysis 16
Automatic HDL Code Generation 16
Integrating Legacy HDL Code 18
Things to remember … 19
IIR Low Pass Filter 21
Hardware Design Challenges: 22
Demo: HDL Workflow Advisor 22
Identifying the critical path 24
Balancing pipeline registers 25
Distributed Pipelining 26
Better Algorithm Design 30
Control Subsystem Execution 31
 Modules can be tri 31
HDL Verification 34
Verification Challenges: 35
Digital Down Converter 36
Integrated HDL Verification 36
HDL Simulator 38
Challenges: 40
Summary: Verification 41
Example MathWorks Services 45
Were Your Expectations Met? 46
Next Steps … 46
Questions? 46

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