MATLAB SIMULINK HDL CODER 1 Manuel d'utilisateur télécharger pdf (Page 40)

9/21/2011

40

Challenges:

Testing algorithms on real hardware

 Motivation:

building confidence

 But …… interfaces with

p

eri

p

herals

86

pp

& rest of the system needed

 Difficult to construct testbenches in

real hardware

Demo: Re-Use System Level test bench

FPGA-in-the-Loop verification

Digital Down Converter

Integration with FPGA

development boards

87

Automatic creation of

FPGA-in-the-Loop

verification models

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